Performance Interconnection Scaling to 1 GHz and Beyond Anthony

Introduction Historically, IBM has made performance the focus of its microelectronics technology strategy. For the wires and insulators used in the back-end-of-the-line (BEOL), this drove the use of damascene tungsten chemical-mechanical polish (CMP) local interconnects and vias, SiO2-based intermetal dielectric CMP planarization, high-aspect ratio aluminum wiring, high-density plasma SiO2 deposition and reactive ion etching, and DUV lithography. To achieve the performance objectives of its 0.25-μm CMOS 6X technology, qualified in 1997, IBM increased the metal line/via aspect ratios by approximately 2X as compared with its 0.50-μm CMOS 5L/5S technologies (Figure 1).